The present invention relates to a semiconductor design technology and, more particularly, to a semiconductor device for generating a multi-phase clock signal, which has a plurality of phase information, with a minimum layout area and optimal current consumption.
Generally, a semiconductor device, such as a DDR SDRAM (Double Data Rate Synchronous DRAM), receives an external clock signal to generate an internal clock signal, and the internal clock signal is inputted to several circuits within the semiconductor device to operate each circuit.
Meanwhile, the current semiconductor device has been developed with the features of large capacity, high speed and low current consumption. Particularly, in order to achieve high speed operation, the semiconductor device is designed to operate in response to the external clock signal having a higher frequency.
Recently, since the frequency of the external clock signal has been raised to a few GHz, the frequency of the internal clock signal is also raised within the semiconductor device, thereby causing many problems in the operation timing margin of a circuit and current consumption.
In order to solve the problems, the semiconductor device employs a method of transferring a multi-phase clock signal. This method is not to transfer a clock signal which has the same high frequency as the external clock signal, but to transfer a plurality of phase clock signals which have a low frequency which corresponds to a half of the high frequency of the external clock signal and have a plurality of phase information, when the internal clock signal is transferred within the semiconductor device. The semiconductor device transfers the internal clock signal by such a method, thereby reducing current consumption caused by internal clock signal transmission and securing a stable timing margin.
Generally, in order to generate the plurality of the phase clock signals, the semiconductor device can include a phase locked loop (PLL) or a delay locked loop (DLL).
FIG. 1 is a block diagram illustrating a conventional phase locked loop for generating a plurality of phase clock signals.
Referring to FIG. 1, the phase locked loop includes a clock frequency divider 110, a control voltage signal generating unit 130 and a voltage control oscillating unit 150.
The clock frequency divider 110 divides a frequency of a reference clock signal CLK_REF which corresponds to an external clock signal. The high frequency of the external clock signal is thus reduced by the clock frequency divider 110.
The control voltage signal generating unit 130 detects a phase of a clock signal generated from the division of the frequency of the reference clock signal CLK_REF by the clock frequency divider 110 and from a phase of a feedback clock signal CLK_FED, thereby generating a control voltage signal V_CTR which has a voltage level corresponding to that of the feedback clock signal CLK_FED.
The voltage control oscillating unit 150 generates a plurality of phase clock signals each having a frequency corresponding to the control voltage signal V_CTR, namely, first to fourth phase clock signals MCLK0, MCLK90, MCLK180 and MCLK270. Among the first to fourth phase clock signals MCLK0, MCLK90, MCLK180 and MCLK270, the third phase clock signal MCLK180 becomes the feedback clock signal CLK_FED which is fed back to the control voltage signal generating unit 130.
The phase locked loop repetitively compares the phase of the clock signal generated from the division of the frequency of the reference clock signal CLK_REF with that of the feedback clock signal CLK_FED in order to generate the first to fourth phase clock signals MCLK0, MCLK90, MCLK180 and MCLK270 each of which has a desired frequency. The finally generated first to fourth phase clock signals MCLK0, MCLK90, MCLK180 and MCLK270 have a constant phase difference and a frequency lower than that of the external clock signal. That is, the second phase clock signal MCLK90 is 90° out of phase with the first phase clock signal MCLK0, the third phase clock signal MCLK180 is 180° out of phase with the first phase clock signal MCLK0, and the fourth phase clock signal MCLK270 is 270° out of phase with the first phase clock signal MCLK0.
Here, since the technical implementation and the operation of the clock frequency divider 110, the control voltage signal generating unit 130 and the voltage control oscillating unit 150 are obvious to those skilled in the art, a detailed explanation for them will not be described.
Meanwhile, generally, the voltage control oscillating unit 150 includes a plurality of delay cells (not illustrated), and the first to fourth phase clock signals MCLK0, MCLK90, MCLK180 and MCLK270 correspond to clock signals outputted from the delay cells. Therefore, in order for the first to fourth phase clock signals MCLK0, MCLK90, MCLK180 and MCLK270 to have an accurate phase difference, the plurality of the delay cells should be identically included and the loadings between the delay cells should be accurately consistent. Also, in order to reduce external noise, a signal or power line should not pass around the voltage control oscillating unit 150. However, such a design has a demerit of occupying too much layout area.
Similar to the phase locked loop, the delay locked loop can also generate the plurality of the phase clock signals. However, there is also a demerit in that the delay locked loop is difficult to design and occupies too much layout area. Also, the phase locked loop and the delay locked loop cause much current consumption during circuit operation.
As described above, the phase locked loop and the delay locked loop, which can generate the plurality of the phase clock signals, have demerits in that there are lots of things to be considered when designing them, they occupy too much layout area, and they consume too much current during circuit operation. Thus, they are an obstacle to low current consumption and high integration in the semiconductor device. The present invention will suggest a solution for such problems.